mirror of
https://github.com/dancojocaru2000/logic-circuits-simulator.git
synced 2025-02-22 17:19:36 +02:00
Fix simulation bug due to missing await
This commit is contained in:
parent
1e65e42115
commit
4a6caee702
1 changed files with 8 additions and 3 deletions
|
@ -30,11 +30,16 @@ class SimulatedComponent {
|
||||||
}
|
}
|
||||||
|
|
||||||
Future<Map<String, bool>> simulate(Map<String, bool> inputs) async {
|
Future<Map<String, bool>> simulate(Map<String, bool> inputs) async {
|
||||||
final input = int.parse(component.inputs.map((input) => inputs[input]! ? '1' : '0').join(), radix: 2);
|
final input = int.parse(
|
||||||
|
component.inputs.map((input) => inputs[input]! ? '1' : '0').join(),
|
||||||
|
radix: 2,
|
||||||
|
);
|
||||||
if (component.truthTable != null) {
|
if (component.truthTable != null) {
|
||||||
final output = component.truthTable![input];
|
final output = component.truthTable![input];
|
||||||
return {
|
return {
|
||||||
for (final it in component.outputs.indexedMap((index, outName) => [outName, output[index]]))
|
for (final it in component.outputs.indexedMap(
|
||||||
|
(index, outName) => [outName, output[index]]
|
||||||
|
))
|
||||||
it[0] : it[1] == '1'
|
it[0] : it[1] == '1'
|
||||||
};
|
};
|
||||||
}
|
}
|
||||||
|
@ -62,7 +67,7 @@ class SimulatedComponent {
|
||||||
// Create instances
|
// Create instances
|
||||||
final wiring = state!.wiring;
|
final wiring = state!.wiring;
|
||||||
for (final instance in wiring.instances) {
|
for (final instance in wiring.instances) {
|
||||||
_getInstance(instance.instanceId, instance.componentId);
|
await _getInstance(instance.instanceId, instance.componentId);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Simulate
|
// Simulate
|
||||||
|
|
Loading…
Add table
Reference in a new issue